Diode-transistor logic

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Simplified schematic of two input DTL NAND gate.

Diode-Transistor Logic (DTL) is a class of digital circuits built from bipolar junction transistors (BJT), diodes and resistors; it is the direct ancestor of transistor-transistor logic. It is called diode-transistor logic because the logic gating function (e.g. AND) is performed by a diode network and the amplifying function is performed by a transistor (contrast this with RTL and TTL).

[edit] Operation

With the simplified circuit shown in the picture the voltage at the base will be near 0.7 volts even when one input is held at ground level, which results in unstable or invalid operation. Two diodes in series are commonly used to lower the voltage and prevent any base current when one or more inputs are at low logic level. The IBM 1401 used DTL circuits almost identical to this simplified circuit, but solved the base bias level problem mentioned above by alternating NPN and PNP based gates operating on different power supply voltages instead of adding extra diodes.

[edit] Advantages and disadvantages

A major advantage over the earlier resistor-transistor logic is the increased Fan-In. The propagation delay is still relatively big, mainly because the base charge having to leak out before the transistor can stop conducting. In practice this delay is often decreased by connecting the base of the transistor through a resistor to ground or a negative voltage.

A problem with DTL is that when the transistor goes into saturation from all inputs being high this results in charge being stored in the base region. So when it comes out of saturation (one input goes low) this charge has to be removed and will dominate the propagation time. One way to speed it up is to connect a resistor to a negative voltage at the base of the transistor which aids the removal of the minority carriers from the base.

Both of the above problems are simultaneously solved in TTL by replacing the diodes of the DTL circuit with a multiple-emitter transistor, which also slightly reduces the required die area per gate in an integrated circuit implementation.